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TM
HMA510
16 x 16-Bit CMOS Parallel Multiplier Accumulator
Description
The HMA510 is a high speed, low power CMOS 16 x 16-bit parallel multiplier accumulator capable of operating at 45ns clocked multiply-accumulate cycles. The 16-bit X and Y operands may be specified as either two's complement or unsigned magnitude format. Additional inputs are provided for the accumulator functions which include: loading the accumulator with the current product, adding or subtracting the accumulator contents and the current product, and preloading the Accumulator Registers from the external inputs. All inputs and outputs are registered. The registers are all positive edge triggered, and are latched on the rising edge of the associated clock signal. The 35-bit Accumulator Output Register is broken into three parts. The 16-bit least significant product (LSP), the 16-bit most significant product (MSP), and the 3-bit extended product (XTP) Registers. The XTP and MSP Registers have dedicated output ports, while the LSP Register shares the Y-inputs in a multiplexed fashion. The entire 35-bit Accumulator Output Register may be preloaded at any time through the use of the bidirectional output ports and the preloaded control.
April 1997
Features
* 16 x 16-Bit Parallel Multiplication with Accumulation to a 35-Bit Result * High-Speed (45ns) Multiply Accumulate Time * Low Power CMOS Operation - ICCSB = 500A Maximum - ICCOP = 7.0mA Maximum at 1.0MHz * HMA510 is Compatible with the CY7C510 and the IDT7210 * Supports Two's Complement or Unsigned Magnitude Operations * TTL Compatible Inputs/Outputs * Three-State Outputs
Ordering Information
PART NUMBER HMA510JC-45 HMA510JC-55 HMA510GC-55 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 PACKAGE 68 Ld PLCC 68 Ld PLCC 68 Ld CPGA PKG. NO. N68.95 N68.95 G68.B
Block Diagram
X0-15 16 RND TC SUB Y0-15 P0-15 16
ACC
REGISTER CLKY CLKX
REGISTER
REGISTER
MULTIPLIER ARRAY 35 PRELOAD CLKP XTP REGISTER ACCUMULATOR MSP REGISTER 3 LSP REGISTER 16 35
16
OEX OEM OEL
P32-34 P16-31
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001. All Rights Reserved
File Number
2806.2
1
HMA510 Pinouts
68 LEAD PLCC TOP VIEW
X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y0/P0 Y1/P1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 X15 OEL RND SUB ACC CLKX CLKY VCC VCC VCC VCC TC OEX PREL OEM CLKP P34 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Y2/P2 Y3/P3 Y4/P4 Y5/P5 Y6/P6 Y7/P7 GND GND Y8/P8 Y9/P9 Y10/P10 Y11/P11 Y12/P12 Y13/P13 Y14/P14 Y15/P15 P16
68 LEAD CPGA TOP VIEW
11
N/C
X15
RND
ACC
CLKY
TC
PREL
CLKP
P33
10
X13
X14
OEL
SUB
CLKX
VCC
OEX
OEM
P34
P32
N/C
9
X11
X12
P30
P31
8
X9
X10
P28
P29
7
X7
X8
P26
P27
6
X5
X6
P24
P25
5
X3
X4
P22
P23
4
X1
X2
P20
P21
3
Y0/P0
X0 Y10/ P10 Y11/ P11 G Y12/ P12 Y13/ P13 H Y14/ P14 Y15/ P15 J
P18
P19
2
N/C
Y1/P1
Y3/P3 Y5/P5
Y7/P7 Y8/P8
P16
P17
1 A
Y2/P2 B
Y4/P4 Y6/P6 C D
GND E
Y9/P9 F
N/C K L
2
HMA510 Pin Descriptions
NAME VCC PLCC PIN NUMBER 17-20 TYPE DESCRIPTION The +5V power supply pins. 0.1F capacitors between the VCC and GND pins are recommended. The device ground. I X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement or unsigned magnitude format. Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's complement or unsigned magnitude format. It may also be used for output of the Least Significant Product (P0-P15) or for preloading the LSP Register. MSP Output Data. This 16-bit port is used to provide the Most Significant Product Output (P16-P31). It may also be used to preload the MSP Register. XTP Output Data. This 3-bit port is used to provide the Extended Product Output (P32P34). It may also be used to preload the XTP Register. Two's Complement Control. Input data is interpreted as two's complement when this control is HIGH. A LOW indicates the data is to be interpreted as unsigned magnitude format. This control is latched on the rising edge of CLKX or CLKY. Accumulate Control. When this control is HIGH, the Accumulator Output Register contents are added to or subtracted from the current product, and the result is stored back into the accumulator Output Register. When LOW, the product is loaded into the accumulator Output Register overwriting the current contents. This control is also latched on the rising edge of CLKX or CLKY. SUB 13 I Subtract Control. When both SUB and ACC are HIGH, the Accumulator Register contents are subtracted from the current product. When ACC is HIGH and SUB is LOW, the Accumulator Register contents and the current product are summed. The SUB control input is latched on the rising edge of CLKX or CLKY. Round Control. When this control is HIGH, a one is added to the most significant bit of the LSP. When LOW, the product is unchanged. Preload Control. When this control is HIGH, the three bidirectional ports may be used to preload the Accumulator Registers. The three-state controls (OEX, OEM, OEL) must be HIGH, and the data will be preloaded on the rising edge of CLKP. When this control is LOW, the Accumulator Registers function in a normal manner. Y-Input/LSP Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high impedance state. This state is required for Y-data input or preloading the LSP Register. When OEL is LOW, the port is enabled for LSP output. MSP Output Port Three-State Control. A LOW on this control line enables the port for output. When OEM is HIGH, the output drivers are in the high impedance state. This control must be HIGH for preloading the MSP Register. XTP Output Port Three-State Control. A LOW on this control line enables the port for output. When OEX is HIGH, the output drivers are in the high impedance state. This control must be HIGH for preloading the XTP Register. X-Register Clock. The rising edge of this clock latches the X-Data Input Register along with the TC, ACC, SUB and RND inputs. Y-Register Clock. The rising edge of this clock latches the Y-Data Input Register along with the TC, ACC, SUB and RND inputs. Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP Registers. If the preload control is active, the data on the I/O ports is loaded into these registers. If preload is not active, the accumulated product is loaded into the registers.
GND X0-X15
53, 54 1-10, 63-68
Y0-Y15/ P0-P15
45-52, 55-62
I/O
P16-P3
29-44
I/O
P32-P34
26-28
I/O
TC
21
I
ACC
14
I
RND
12
I
PREL
23
I
OEL
11
I
OEM
24
I
OEX
22
I
CLKX
15
I
CLKY
16
I
CLKP
25
I
3-3
HMA510 Functional Description
The HMA510 is a high speed 16 x 16-bit multiplier accumulator (MAC). It consists of a 16-bit parallel multiplier follower by a 35-bit accumulator. All inputs and outputs are registered and are latched on the rising edge of the associated clock signal. The HMA510 is divided into four sections: the input section, the multiplier array, the accumulator and the output/preload section. The input section has two 16-bit Operand Input Registers for the X and Y operands which are latched on the rising edge of CLKX and CLKY respectively. A four bit Control Register (TC, RND, ACC, SUB) is also included and is latched from either of the input clock signals. The 16 x 16 multiplier array produces the 32-bit product of the input operands. Two's complement or unsigned magnitude operation can be selected by the use of the TC control. The 32-bit result may also be rounded through the use of the RND control. In this case, a `1' is added to the MSB of the LSP (bit P15). The 32-bit product is zero-filled or signextended as appropriate and passed as a 35-bit number to the accumulator section. The accumulator functions are controlled by the ACC, SUB and PREL control inputs. Four functions may be selected: the accumulator may be loaded with the current product; the product may be added to the accumulator contents; the accumulator contents may be subtracted from the current product; or the accumulator may be loaded from the bidirectional ports. The Accumulator Registers are updated at the rising edge of the CLKP signal. The output/preload section contains the Accumulator/Output Register and the bidirectional ports. This section is controlled by the signals PREL, OEX, OEM and OEL. When PREL is high, the output buffers are in a high impedance state. When one of the controls OEX, OEM or OEL are also high, data present at the outputs will be preloaded into the associated register on the rising edge of CLKP. When PREL is low, the signals OEX, OEM and OEL are enable controls for their respective three-state output ports.
TABLE 1. PRELOAD FUNCTION TABLE OUTPUT REGISTERS PREL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OEX 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OEM 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OEL 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XTP Q Q Q Q Z Z Z Z Z Z Z Z PL PL PL PL MSP Q Q Z Z Q Q Z Z Z Z PL PL Z Z PL PL LSP Q Z Q Z Q Z Q Z Z PL Z PL Z PL Z PL
Z = Output Buffers at High Impedance (Disabled). Q = Output Buffers at LOW Impedance. Contents of Output Register Available Through Output Ports. PL = Output disabled. Preload data supplied to the output pins will be loaded into the register at the rising edge of CLKP. TABLE 2. ACCUMULATOR FUNCTION TABLE PREL L L L H ACC L H H X SUB X L H X P Q Q Q PL Load Add Subtract Preload OPERATION
4
HMA510 Input Formats
X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 Y 7 6 5 4 3 2 1 0
-20 2-1 2-2 2 -3 2-4 2-5 2-6 2-7 2 -8 2-9 2-10 2 -11 2-12 2-13 2-14 2-15 (SIGN)
-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2 -9 2-10 2-11 2 -12 2-13 2-14 2-15 (SIGN)
FIGURE 1. FRACTIONAL TWO's COMPLEMENT INPUT
X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 Y 7 6 5 4 3 2 1 0
2-15 2-14 2 -13 2-12 2-11 2-10 2-9 2 -8 2-7 2-6 2-5 2-4 2 -3 2-2 2-1 -20 (SIGN)
2-15 2-14 2-13 2-12 2 -11 2-10 2-9 2-8 2-7 2 -6 2-5 2-4 2-3 2 -2 2-1 -2 0 (SIGN)
FIGURE 2. INTEGER TWO'S COMPLEMENT INPUT
X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 Y 7 6 5 4 3 2 1 0
2-1 2-2 2-3 2 -4 2-5 2-6 2-7 2-8 2 -9 2-10 2-11 2 -12 2-13 2-14 2-15 2-16
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2 -10 2-11 2-12 2 -13 2-14 2-15 2-16
FIGURE 3. UNSIGNED FRACTIONAL INPUT
X 15 14 13 12 11 10 9 29 8 28 7 27 6 26 5 25 4 24 3 23 2 22 1 21 0 20 15 14 13 12 11 10 9 8 28
Y 7 27 6 26 5 25 4 24 3 23 2 22 1 21 0 20
2 15 214 213 212 211 210
215 214 213 212 211 2 10 29
FIGURE 4. UNSIGNED INTEGER INPUT
Output Formats
XTP 34 33 32 22 MSP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2 -12 2 -13 2-14 15 14 13 12 11 10 9 LSP 8 7 6 5 4 3 2 1 0
-24 23 (SIGN)
2-15 2-14 2-13 2-12 2 -11 2-10 2-9 2-8 2-7 2 -6 2-5 2-4 2-3 2-2 2 -1 -20
FIGURE 5. TWO'S COMPLEMENT FRACTIONAL OUTPUT
XTP 34 33 32
MSP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 15 14 13 12 11 10 9
LSP 8 7 6 5 4 3 2 1 0
-234 2 33 2 32 (SIGN)
215 214 2 13 212 211 2 10 29 28 2 7 26 25 24 23 2 2 21 20
FIGURE 6. TWO'S COMPLEMENT INTEGER OUTPUT
XTP 34 22 33 21 32 20
MSP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 2-12-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-11 2-12 2-13 2 -14 2 -15 2-16 15 14 13 12 11 10 9
LSP 8 7 6 5 4 3 2 1 0
2-17 2-18 2-19 2-20 2 -21 2-222-23 -242-252-262-272 -28 -292-302-31 -2 32 2 2
FIGURE 7. UNSIGNED FRACTIONAL OUTPUT
3-5
HMA510 Output Formats
XTP 34 33 32 MSP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 15 14 13 12 11 10 9 LSP 8 7 6 5 4 3 2 1 0
234 2 33 2 32
215 214 2 13 212 211 2 10 29 28 2 7 26 25 24 23 2 2 21 20
FIGURE 8. UNSIGNED INTEGER OUTPUT
6
HMA510
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied. . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA(oC/W) JC (oC/W) 68 Lead PLCC . . . . . . . . . . . . . . . . . . . 43.2 15.1 68 Lead PGA . . . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Package Power Dissipation at 70oC PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7W PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.46/W Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4800 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications VCC = 5.0V 5%, TA = 0oC to 70oC
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output or I/O Leakage Current Standby Power Supply Current SYMBOL VIH V IL V OH VOL II IO ICCSB ICCOP TEST CONDITIONS VCC = 5.25V VCC = 4.75V IOH = -400mA, VCC = 4.75V IOL = +4.0mA, VCC = 4.75V VIN = VCC or GND, VCC = 5.25V VOUT = VCC or GND, VCC = 5.25V VIN = VCC or GND, VCC = 5.25V, Outputs Open f = 1.0MHz, VIN = VCC or GND VCC = 5.25V (Note 2) MIN 2.0 2.6 -10 -10 MAX 0.8 0.4 10 10 500 UNITS V V V V A A A
Operating Power Supply Current
-
7.0
mA
NOTE: 2. Operating Supply Current is proportional to frequency, typical rating is 5.0mA/MHz.
Capacitance TA = 25oC, Note 3
PARAMETER Input Capacitance Output Capacitance I/O Capacitance NOTES: 3. Not tested, but characterized at initial design and at major process/design changes. SYMBOL CIN COUT CI/O TEST CONDITIONS FREQ = 1MHz, VCC = Open all Measurements are Referenced to Device Ground MIN MAX 10 10 15 UNITS pF pF pF
AC Electrical Specifications VCC = 5.0V 5%, TA = 0oC to 70oC
HMA510-45 PARAMETER Multiply Accumulate Time SYMBOL TMA TEST CONDITIONS MIN MAX 45 HMA510-55 MIN MAX 55 UNITS ns
3-7
AC Electrical Specifications VCC = 5.0V 5%, TA = 0oC to 70oC (Continued)
HMA510-45 PARAMETER Output Delay Three-State Enable Time Three-State Disable Time Input Setup Time Input Hold Time Clock High Pulse Width Clock Low Pulse Width Output Rise Time Output Fall Time NOTES: 4. Transition is measured at 200mV from steady state voltage with loading specified in AC Test Circuit; V1 = 1.5V, R1 = 500 and CL = 40pF. 5. For AC Test load, refer to AC Test Circuit with V1 = 2.4V, R1 = 500 and CL = 40pF. SYMBOL TD TENA TDIS TS TH TPWH TPWL tR tF From 0.8V to 2.0V From 2.0V to 0.8V Note 4 Note 4 TEST CONDITIONS MIN 18 2 15 15 MAX 25 25 25 8 8 HMA510-55 MIN 20 2 20 20 MAX 30 30 30 8 8 UNITS ns ns ns ns ns ns ns ns ns
AC Test Circuit
V1 R1
AC Testing Input, Output Waveforms
0.3V DUT C 1 (SEE NOTE) 0V
1.5V
1.5V
VOH VOL
NOTE: Includes Stray and Jig Capacitance
NOTE: AC Testing: All Parameters tested as per test circuit. Input rise and fall times are driven at 1ns/V.
Timing Diagram
DATA INPUT 3.0V 1.5V 0V 3.0V 1.5V 0V THREE STATE CONTROL tDIS OUTPUT THREE STATE tENA 1.5V
tS
tH
CLOCK INPUT
HIGH IMPEDANCE
FIGURE 9. SETUP AND HOLD TIME
FIGURE 10. THREE-STATE CONTROL
8
Timing Diagram
tPWL tPWH CLKX CLKY XIN, YIN RND, TC ACC, SUB CLKP tS tHCL tPWH tH CLKP tMA tD PREL OEX OEM OEL OUTPUT PINS tPWL
tS
tH
OUTPUT P, Y
FIGURE 11. HMA510 TIMING DIAGRAM
FIGURE 12. PRELOAD TIMING DIAGRAM
3-9
HMA510
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